AT91SAM
ARM-based
Flash MCU
SAM3X
SAM3A
Series
Features
• Core
– ARM® Cortex®-M3 revision 2.0 running at up to 84 MHz
– Memory Protection Unit (MPU)
– Thumb®-2 instruction set
– 24-bit SysTick Counter
– Nested Vector Interrupt Controller
• Memories
– From 256 to 512 Kbytes embedded Flash, 128-bit wide access, memory accelerator, dual bank
– From 32 to 100 Kbytes embedded SRAM with dual banks
– 16 Kbytes ROM with embedded bootloader routines (UART, USB) and IAP routines
– Static Memory Controller (SMC): SRAM, NOR, NAND support. NAND Flash
controller with 4-kbyte RAM buffer and ECC
• System
– Embedded voltage regulator for single supply operation
– POR, BOD and Watchdog for safe reset
– Quartz or ceramic resonator oscillators: 3 to 20 MHz main and optional low power
32.768 kHz for RTC or device clock.
– High precision 8/12 MHz factory trimmed internal RC oscillator with 4 MHz Default
Frequency for fast device startup
– Slow Clock Internal RC oscillator as permanent clock for device clock in low power
mode
– One PLL for device clock and one dedicated PLL for USB 2.0 High Speed Mini
Host/Device
– Temperature Sensor
– Up to 17 peripheral DMA (PDC) channels and 6-channel central DMA plus
dedicated DMA for High-Speed USB Mini Host/Device and Ethernet MAC
• Low Power Modes
– Sleep and Backup modes, down to 2.5 μA in Backup mode.
– Backup domain: VDDBU pin, RTC, eight 32-bit backup registers
– Ultra Low-power RTC
• Peripherals
– USB 2.0 Device/Mini Host: 480 Mbps, 4-kbyte FIFO, up to 10 bidirectional
Endpoints, dedicated DMA
– Up to 4 USARTs (ISO7816, IrDA®, Flow Control, SPI, Manchester and LIN support)
and one UART
– 2 TWI (I2C compatible), up to 6 SPIs, 1 SSC (I2S), 1 HSMCI (SDIO/SD/MMC) with up
to 2 slots
– 9-Channel 32-bit Timer/Counter (TC) for capture, compare and PWM mode,
Quadrature Decoder Logic and 2-bit Gray Up/Down Counter for Stepper Motor
– Up to 8-channel 16-bit PWM (PWMC) with Complementary Output, Fault Input, 12-
bit Dead Time Generator Counter for Motor Control
– 32-bit Real Time Timer (RTT) and RTC with calendar and alarm features
– 16-channel 12-bit 1Msps ADC with differential input mode and programmable gain
stage
– One 2-channel 12-bit 1 MSPS DAC
– One Ethernet MAC 10/100 (EMAC) with dedicated DMA
– Two CAN Controller with eight Mailboxes
– One True Random Number Generator (TRNG)
– Write Protected Registers
• I/O
– Up to 103 I/O lines with external interrupt capability (edge or level sensitivity),
debouncing, glitch filtering and on-die Series Resistor Termination
– Up to Six 32-bit Parallel Input/Outputs (PIO)
• Packages
– 100-lead LQFP, 14 x 14 mm, pitch 0.5 mm
– 100-ball LFBGA, 9 x 9 mm, pitch 0.8 mm
– 144-lead LQFP, 20 x 20 mm, pitch 0.5 mm
– 144-ball LFBGA, 10 x 10 mm, pitch 0.8 mm
Click here to download ATMEL pdf datasheets AT91SAM ARM-based Flash MCU SAM3X SAM3A Series
TopDatasheet-IC chip circuits ATMEL Quantum pdf datasheets download
Showing posts with label S. Show all posts
Showing posts with label S. Show all posts
Sunday, May 12, 2013
STK500 User Guide download ATMEL pdf datasheets
STK500
..............................................................................................
User Guide
Introduction
Congratulations on your purchase of the AVR?STK500 Flash Microcontroller Starter
Kit. The STK500 is a complete starter kit and development system for the AVR Flash
Microcontroller from Atmel Corporation. It is designed to give designers a quick start to
develop code on the AVR and for prototyping and testing of new designs.
1.1 Starter Kit
Features
AVR Studio?Compatible
RS-232 Interface to PC for Programming and Control
Regulated Power Supply for 10 - 15V DC Power
Sockets for 8-pin, 20-pin, 28-pin, and 40-pin AVR Devices
Parallel and Serial High-voltage Programming of AVR Devices
Serial In-System Programming (ISP) of AVR Devices
In-System Programmer for Programming AVR Devices in External Target System
Reprogramming of AVR Devices
8 Push Buttons for General Use
8 LEDs for General Use
All AVR I/O Ports Easily Accessible through Pin Header Connectors
Additional RS-232 Port for General Use
Expansion Connectors for Plug-in Modules and Prototyping Area
(NB! No longer valid: "On-board 2-Mbit DataFlash?for Nonvolatile Data Storage")
The STK500 is supported by AVR Studio, version 3.2 or higher. For up-to-date information
on this and other AVR tool products, please read the document 揳vrtools.pdf? The
newest version of AVR Studio, 揳vrtools.pdf?and this user guide can be found in the
AVR section of the Atmel web site, www.atmel.com.
Click here to download ATMEL pdf datasheets STK500 User
TopDatasheet-IC chip circuits ATMEL Quantum pdf datasheets download
..............................................................................................
User Guide
Introduction
Congratulations on your purchase of the AVR?STK500 Flash Microcontroller Starter
Kit. The STK500 is a complete starter kit and development system for the AVR Flash
Microcontroller from Atmel Corporation. It is designed to give designers a quick start to
develop code on the AVR and for prototyping and testing of new designs.
1.1 Starter Kit
Features
AVR Studio?Compatible
RS-232 Interface to PC for Programming and Control
Regulated Power Supply for 10 - 15V DC Power
Sockets for 8-pin, 20-pin, 28-pin, and 40-pin AVR Devices
Parallel and Serial High-voltage Programming of AVR Devices
Serial In-System Programming (ISP) of AVR Devices
In-System Programmer for Programming AVR Devices in External Target System
Reprogramming of AVR Devices
8 Push Buttons for General Use
8 LEDs for General Use
All AVR I/O Ports Easily Accessible through Pin Header Connectors
Additional RS-232 Port for General Use
Expansion Connectors for Plug-in Modules and Prototyping Area
(NB! No longer valid: "On-board 2-Mbit DataFlash?for Nonvolatile Data Storage")
The STK500 is supported by AVR Studio, version 3.2 or higher. For up-to-date information
on this and other AVR tool products, please read the document 揳vrtools.pdf? The
newest version of AVR Studio, 揳vrtools.pdf?and this user guide can be found in the
AVR section of the Atmel web site, www.atmel.com.
Click here to download ATMEL pdf datasheets STK500 User
TopDatasheet-IC chip circuits ATMEL Quantum pdf datasheets download
Saturday, May 11, 2013
STK501 User Guide download ATMEL pdf datasheets
STK501
.............................................................................
User Guide
Introduction
The STK501 board is a top module designed to add ATmega103(L) and ATmega128(L)
support to the STK500 development board from Atmel Corporation. With this board the
STK500 is extended to support all current AVR devices in a single development
environment.
The STK501 includes connectors, jumpers and hardware allowing full utilization of the
new features of the ATmega128(L) while the Zero Insertion Force (ZIF) socket allows
easy use of TQFP packages for prototyping.
This user guide acts as a general getting started guide as well as a complete technical
reference for advanced users.
In addition to adding support for new devices, it also adds new support for peripherals
previously not supported by the STK500. An additional RS-232 port and external SRAM
interface are09/01 among the new features. Devices with dual UART or XRAM interface
can all take advantage of the new resources on the STK501 board.
Features
STK500 Compatible
AVR Studio® Compatible
Supports ATmega103(L) and ATmega128(L)
Zero Insertion Force Socket for TQFP Packages
TQFP Footprint for Emulator Adapters
Supports all Added Features in ATmega128(L)
JTAG Connector for On-chip Debugging Using JTAG ICE (ATmega128(L))
Additional RS-232C Port with Available RTS/CTS Handshake Lines
Adds External SRAM Support to the STK500 Board (Usable for all Devices with
XRAM Interface)
On-board 32 kHz Crystal for Easy RTC Implementations
Click here to download ATMEL pdf datasheets STK501 User Guide
TopDatasheet-IC chip circuits ATMEL Quantum pdf datasheets download
.............................................................................
User Guide
Introduction
The STK501 board is a top module designed to add ATmega103(L) and ATmega128(L)
support to the STK500 development board from Atmel Corporation. With this board the
STK500 is extended to support all current AVR devices in a single development
environment.
The STK501 includes connectors, jumpers and hardware allowing full utilization of the
new features of the ATmega128(L) while the Zero Insertion Force (ZIF) socket allows
easy use of TQFP packages for prototyping.
This user guide acts as a general getting started guide as well as a complete technical
reference for advanced users.
In addition to adding support for new devices, it also adds new support for peripherals
previously not supported by the STK500. An additional RS-232 port and external SRAM
interface are09/01 among the new features. Devices with dual UART or XRAM interface
can all take advantage of the new resources on the STK501 board.
Features
STK500 Compatible
AVR Studio® Compatible
Supports ATmega103(L) and ATmega128(L)
Zero Insertion Force Socket for TQFP Packages
TQFP Footprint for Emulator Adapters
Supports all Added Features in ATmega128(L)
JTAG Connector for On-chip Debugging Using JTAG ICE (ATmega128(L))
Additional RS-232C Port with Available RTS/CTS Handshake Lines
Adds External SRAM Support to the STK500 Board (Usable for all Devices with
XRAM Interface)
On-board 32 kHz Crystal for Easy RTC Implementations
Click here to download ATMEL pdf datasheets STK501 User Guide
TopDatasheet-IC chip circuits ATMEL Quantum pdf datasheets download
Friday, October 5, 2012
sn74221 Texas Instruments TI pdf datasheet download
sn74221
Dual Versions of Highly Stable SN54121
and SN74121 One Shots
SN54221 and SN74221 Demonstrate
Electrical and Switching Characteristics
That Are Virtually Identical to the SN54121
and SN74121 One Shots
Pinout Is Identical to the SN54123,
SN74123, SN54LS123, and SN74LS123
Overriding Clear Terminates Output Pulse
description/ordering information
The ’221 and ’LS221 devices are dual
multivibrators with performance characteristics
virtually identical to those of the ’121 devices.
Each multivibrator features a negative-transitiontriggered
input and a positive-transition-triggered
input, either of which can be used as an inhibit
input.
Pulse triggering occurs at a particular voltage level and is not directly related to the transition time of the input
pulse. Schmitt-trigger input circuitry (TTL hysteresis) for B input allows jitter-free triggering from inputs with
transition at rates as slow as 1 V/s, providing the circuit with excellent noise immunity, typically of 1.2 V. A high
immunity to VCC noise, typically of 1.5 V, also is provided by internal latching circuitry.
Once fired, the outputs are independent of further transitions of the A and B inputs and are a function of the timing
components, or the output pulses can be terminated by the overriding clear. Input pulses can be of any duration
relative to the output pulse. Output pulse length can be varied from 35 ns to the maximum by choosing
appropriate timing components. With Rext = 2 kΩ and Cext = 0, an output pulse typically of 30 ns is achieved
that can be used as a dc-triggered reset signal. Output rise and fall times are TTL compatible and independent
of pulse length. Typical triggering and clearing sequences are shown as a part of the switching characteristics
waveforms.
Click here to download sn74221 Texas Instruments TI pdf datasheet
DatasheetDoc-Texas Instruments TI pdf datasheet download
Dual Versions of Highly Stable SN54121
and SN74121 One Shots
SN54221 and SN74221 Demonstrate
Electrical and Switching Characteristics
That Are Virtually Identical to the SN54121
and SN74121 One Shots
Pinout Is Identical to the SN54123,
SN74123, SN54LS123, and SN74LS123
Overriding Clear Terminates Output Pulse
description/ordering information
The ’221 and ’LS221 devices are dual
multivibrators with performance characteristics
virtually identical to those of the ’121 devices.
Each multivibrator features a negative-transitiontriggered
input and a positive-transition-triggered
input, either of which can be used as an inhibit
input.
Pulse triggering occurs at a particular voltage level and is not directly related to the transition time of the input
pulse. Schmitt-trigger input circuitry (TTL hysteresis) for B input allows jitter-free triggering from inputs with
transition at rates as slow as 1 V/s, providing the circuit with excellent noise immunity, typically of 1.2 V. A high
immunity to VCC noise, typically of 1.5 V, also is provided by internal latching circuitry.
Once fired, the outputs are independent of further transitions of the A and B inputs and are a function of the timing
components, or the output pulses can be terminated by the overriding clear. Input pulses can be of any duration
relative to the output pulse. Output pulse length can be varied from 35 ns to the maximum by choosing
appropriate timing components. With Rext = 2 kΩ and Cext = 0, an output pulse typically of 30 ns is achieved
that can be used as a dc-triggered reset signal. Output rise and fall times are TTL compatible and independent
of pulse length. Typical triggering and clearing sequences are shown as a part of the switching characteristics
waveforms.
Click here to download sn74221 Texas Instruments TI pdf datasheet
DatasheetDoc-Texas Instruments TI pdf datasheet download
sn74ls147 Texas Instruments TI pdf datasheet download
sn74ls147
’147, ’LS147
Encode 10-Line Decimal to 4-Line BCD
Applications Include:
− Keyboard Encoding
− Range Selection
’148, ’LS148
Encode 8 Data Lines to 3-Line Binary
(Octal)
Applications Include:
− n-Bit Encoding
− Code Converters and Generators
description/ordering information
These TTL encoders feature priority decoding of the inputs to ensure that only the highest-order data line is
encoded. The ’147 and ’LS147 devices encode nine data lines to four-line (8-4-2-1) BCD. The implied decimal
zero condition requires no input condition, as zero is encoded when all nine data lines are at a high logic level.
The ’148 and ’LS148 devices encode eight data lines to three-line (4-2-1) binary (octal). Cascading circuitry
(enable input EI and enable output EO) has been provided to allow octal expansion without the need for external
circuitry. For all types, data inputs and outputs are active at the low logic level. All inputs are buffered to represent
one normalized Series 54/74 or 54/74LS load, respectively.
Click here to download sn74ls147 Texas Instruments TI pdf datasheet
DatasheetDoc-Texas Instruments TI pdf datasheet download
’147, ’LS147
Encode 10-Line Decimal to 4-Line BCD
Applications Include:
− Keyboard Encoding
− Range Selection
’148, ’LS148
Encode 8 Data Lines to 3-Line Binary
(Octal)
Applications Include:
− n-Bit Encoding
− Code Converters and Generators
description/ordering information
These TTL encoders feature priority decoding of the inputs to ensure that only the highest-order data line is
encoded. The ’147 and ’LS147 devices encode nine data lines to four-line (8-4-2-1) BCD. The implied decimal
zero condition requires no input condition, as zero is encoded when all nine data lines are at a high logic level.
The ’148 and ’LS148 devices encode eight data lines to three-line (4-2-1) binary (octal). Cascading circuitry
(enable input EI and enable output EO) has been provided to allow octal expansion without the need for external
circuitry. For all types, data inputs and outputs are active at the low logic level. All inputs are buffered to represent
one normalized Series 54/74 or 54/74LS load, respectively.
Click here to download sn74ls147 Texas Instruments TI pdf datasheet
DatasheetDoc-Texas Instruments TI pdf datasheet download
Monday, September 24, 2012
SN74LVC4245A Texas Instruments TI pdf datasheet download
SN74LVC4245A
OCTAL BUS TRANSCEIVER AND 3.3-V TO 5-V SHIFTER
WITH 3-STATE OUTPUTS
FEATURES
Bidirectional Voltage Translator
· 5.5 V on A Port and 2.7 V to 3.6 V on B Port
· Control Inputs VIH/VIL Levels Are Referenced
to VCCA Voltage
· Latch-Up Performance Exceeds 250 mA Per
JESD 17
· ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
DESCRIPTION/ORDERING INFORMATION
This 8-bit (octal) noninverting bus transceiver
contains two separate supply rails; B port has VCCB,
which is set at 3.3 V, and A port has VCCA, which is
set at 5 V. This allows for translation from a 3.3-V to
a 5-V environment, and vice versa.
<br/>
The SN74LVC4245A is designed for asynchronous communication between data buses. The device transmits
data from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the
direction-control (DIR) input. The output-enable (OE) input can be used to disable the device so the buses are
effectively isolated. The control circuitry (DIR, OE) is powered by VCCA.
The SN74LVC4245A pinout allows the designer to switch to a normal all-3.3-V or all-5-V 20-pin '245 device
without board re-layout. The designer uses the data paths for pins 2–11 and 14–23 of the SN74LVC4245A to
align with the conventional '245 pinout.
Click here to download SN74LVC4245A Texas Instruments TI pdf datasheet
DatasheetDoc-Texas Instruments TI pdf datasheet download
OCTAL BUS TRANSCEIVER AND 3.3-V TO 5-V SHIFTER
WITH 3-STATE OUTPUTS
FEATURES
Bidirectional Voltage Translator
· 5.5 V on A Port and 2.7 V to 3.6 V on B Port
· Control Inputs VIH/VIL Levels Are Referenced
to VCCA Voltage
· Latch-Up Performance Exceeds 250 mA Per
JESD 17
· ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
DESCRIPTION/ORDERING INFORMATION
This 8-bit (octal) noninverting bus transceiver
contains two separate supply rails; B port has VCCB,
which is set at 3.3 V, and A port has VCCA, which is
set at 5 V. This allows for translation from a 3.3-V to
a 5-V environment, and vice versa.
<br/>
The SN74LVC4245A is designed for asynchronous communication between data buses. The device transmits
data from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the
direction-control (DIR) input. The output-enable (OE) input can be used to disable the device so the buses are
effectively isolated. The control circuitry (DIR, OE) is powered by VCCA.
The SN74LVC4245A pinout allows the designer to switch to a normal all-3.3-V or all-5-V 20-pin '245 device
without board re-layout. The designer uses the data paths for pins 2–11 and 14–23 of the SN74LVC4245A to
align with the conventional '245 pinout.
Click here to download SN74LVC4245A Texas Instruments TI pdf datasheet
DatasheetDoc-Texas Instruments TI pdf datasheet download
SN54165, SN54LS165A, SN74165, SN74LS165A Texas Instruments TI pdf datasheet download
SN54165, SN54LS165A, SN74165, SN74LS165A
PARALLEL-LOAD 8-BIT SHIFT REGISTERS
Complementary Outputs
Direct Overriding Load (Data) Inputs
Gated Clock Inputs
Parallel-to-Serial Data Conversion
description
The ’165 and ’LS165A are 8-bit serial shift
registers that shift the data in the direction of QA
toward QH when clocked. Parallel-in access to
each stage is made available by eight individual,
direct data inputs that are enabled by a low level
at the shift/load (SH/LD) input. These registers
also feature gated clock (CLK) inputs and
complementary outputs from the eighth bit. All
inputs are diode-clamped to minimize
transmission-line effects, thereby simplifying
system design.
Clocking is accomplished through a two-input
positive-NOR gate, permitting one input to be
used as a clock-inhibit function. Holding either of
the clock inputs high inhibits clocking, and holding
either clock input low with SH/LD high enables the
other clock input. Clock inhibit (CLK INH) should
be changed to the high level only while CLK is
high. Parallel loading is inhibited as long as SH/LD
is high. Data at the parallel inputs are loaded
directly into the register while SH/LD is low,
independently of the levels of CLK, CLK INH, or
serial (SER) inputs.
Click here to download SN54165, SN54LS165A, SN74165, SN74LS165A Texas Instruments TI pdf datasheet
DatasheetDoc-Texas Instruments TI pdf datasheet download
PARALLEL-LOAD 8-BIT SHIFT REGISTERS
Complementary Outputs
Direct Overriding Load (Data) Inputs
Gated Clock Inputs
Parallel-to-Serial Data Conversion
description
The ’165 and ’LS165A are 8-bit serial shift
registers that shift the data in the direction of QA
toward QH when clocked. Parallel-in access to
each stage is made available by eight individual,
direct data inputs that are enabled by a low level
at the shift/load (SH/LD) input. These registers
also feature gated clock (CLK) inputs and
complementary outputs from the eighth bit. All
inputs are diode-clamped to minimize
transmission-line effects, thereby simplifying
system design.
Clocking is accomplished through a two-input
positive-NOR gate, permitting one input to be
used as a clock-inhibit function. Holding either of
the clock inputs high inhibits clocking, and holding
either clock input low with SH/LD high enables the
other clock input. Clock inhibit (CLK INH) should
be changed to the high level only while CLK is
high. Parallel loading is inhibited as long as SH/LD
is high. Data at the parallel inputs are loaded
directly into the register while SH/LD is low,
independently of the levels of CLK, CLK INH, or
serial (SER) inputs.
Click here to download SN54165, SN54LS165A, SN74165, SN74LS165A Texas Instruments TI pdf datasheet
DatasheetDoc-Texas Instruments TI pdf datasheet download
Sunday, September 23, 2012
sn74hct14 Texas Instruments TI pdf datasheet download
sn74hct14
Operating Voltage Range of 4.5 V to 5.5 V
Outputs Can Drive Up To 10 LSTTL Loads
Low Power Consumption, 20-μA Max ICC
Typical tpd = 18 ns
±4-mA Output Drive at 5 V
Low Input Current of 1 μA Max
Inputs Are TTL-Voltage Compatible
description/ordering information
The ’HCT14 devices contain six independent inverters. The devices perform the Boolean function Y = A in
positive logic.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to VCC + 0.5 V
Output voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to VCC + 0.5 V
Input clamp current, IIK (VI < 0 or VI > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25 mA
Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Package thermal impedance, θJA (see Note 2): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86°C/W
DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96°C/W
DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127°C/W
N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80°C/W
PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
Click here to download sn74hct14 Texas Instruments TI pdf datasheet
DatasheetDoc-Texas Instruments TI pdf datasheet download
Operating Voltage Range of 4.5 V to 5.5 V
Outputs Can Drive Up To 10 LSTTL Loads
Low Power Consumption, 20-μA Max ICC
Typical tpd = 18 ns
±4-mA Output Drive at 5 V
Low Input Current of 1 μA Max
Inputs Are TTL-Voltage Compatible
description/ordering information
The ’HCT14 devices contain six independent inverters. The devices perform the Boolean function Y = A in
positive logic.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to VCC + 0.5 V
Output voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to VCC + 0.5 V
Input clamp current, IIK (VI < 0 or VI > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25 mA
Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Package thermal impedance, θJA (see Note 2): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86°C/W
DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96°C/W
DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127°C/W
N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80°C/W
PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
Click here to download sn74hct14 Texas Instruments TI pdf datasheet
DatasheetDoc-Texas Instruments TI pdf datasheet download
sn74hc4040 Texas Instruments TI pdf datasheet download
sn74hc4040
Wide Operating Voltage Range of 2 V to 6 V
Outputs Can Drive Up To 10 LSTTL Loads
Low Power Consumption, 80-μA Max ICC
Typical tpd = 12 ns
±4-mA Output Drive at 5 V
Low Input Current of 1 μA Max
description/ordering information
The ’HC4040 devices are 12-stage asynchronous binary counters, with the outputs of all stages available
externally. A high level at the clear (CLR) input asynchronously clears the counter and resets all outputs low.
The count is advanced on a high-to-low transition at the clock (CLK) input. Applications include time-delay
circuits, counter controls, and frequency-dividing circuits.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Input clamp current, IIK (VI < 0 or VI > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
Output clamp current, IOK (VO < 0 or VO > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25 mA
Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
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Wide Operating Voltage Range of 2 V to 6 V
Outputs Can Drive Up To 10 LSTTL Loads
Low Power Consumption, 80-μA Max ICC
Typical tpd = 12 ns
±4-mA Output Drive at 5 V
Low Input Current of 1 μA Max
description/ordering information
The ’HC4040 devices are 12-stage asynchronous binary counters, with the outputs of all stages available
externally. A high level at the clear (CLR) input asynchronously clears the counter and resets all outputs low.
The count is advanced on a high-to-low transition at the clock (CLK) input. Applications include time-delay
circuits, counter controls, and frequency-dividing circuits.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Input clamp current, IIK (VI < 0 or VI > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
Output clamp current, IOK (VO < 0 or VO > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25 mA
Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
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sn74hc373 Texas Instruments TI pdf datasheet download
sn74hc373
Wide Operating Voltage Range of 2 V to 6 V
High-Current 3-State True Outputs Can
Drive Up To 15 LSTTL Loads
Low Power Consumption, 80-μA Max ICC
Typical tpd = 13 ns
±6-mA Output Drive at 5 V
Low Input Current of 1 μA Max
Eight High-Current Latches in a Single
Package
Full Parallel Access for Loading
description/ordering information
These 8-bit latches feature 3-state outputs designed specifically for driving highly capacitive or relatively
low-impedance loads. They are particularly suitable for implementing buffer registers, I/O ports, bidirectional
bus drivers, and working registers.
The eight latches of the ’HC373 devices are transparent D-type latches. While the latch-enable (LE) input is
high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the levels that
were set up at the D inputs.
An output-enable (OE) input places the eight outputs in either a normal logic state (high or low logic levels) or
the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines
significantly. The high-impedance state and increased drive provide the capability to drive bus lines without
interface or pullup components.
OE does not affect the internal operations of the latches. Old data can be retained or new data can be entered
while the outputs are off.
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Wide Operating Voltage Range of 2 V to 6 V
High-Current 3-State True Outputs Can
Drive Up To 15 LSTTL Loads
Low Power Consumption, 80-μA Max ICC
Typical tpd = 13 ns
±6-mA Output Drive at 5 V
Low Input Current of 1 μA Max
Eight High-Current Latches in a Single
Package
Full Parallel Access for Loading
description/ordering information
These 8-bit latches feature 3-state outputs designed specifically for driving highly capacitive or relatively
low-impedance loads. They are particularly suitable for implementing buffer registers, I/O ports, bidirectional
bus drivers, and working registers.
The eight latches of the ’HC373 devices are transparent D-type latches. While the latch-enable (LE) input is
high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the levels that
were set up at the D inputs.
An output-enable (OE) input places the eight outputs in either a normal logic state (high or low logic levels) or
the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines
significantly. The high-impedance state and increased drive provide the capability to drive bus lines without
interface or pullup components.
OE does not affect the internal operations of the latches. Old data can be retained or new data can be entered
while the outputs are off.
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sn74hc273 Texas Instruments TI pdf datasheet download
sn74hc273
Wide Operating Voltage Range of 2 V to 6 V
Outputs Can Drive Up To 10 LSTTL Loads
Low Power Consumption, 80-μA Max ICC
Typical tpd = 12 ns
±4-mA Output Drive at 5 V
Low Input Current of 1 μA Max
Contain Eight Flip-Flops With Single-Rail
Outputs
Direct Clear Input
Individual Data Input to Each Flip-Flop
Applications Include:
− Buffer/Storage Registers
− Shift Registers
− Pattern Generators
description/ordering information
These circuits are positive-edge-triggered D-type flip-flops with a direct clear (CLR) input.
Information at the data (D) inputs meeting the setup time requirements is transferred to the Q outputs on the
positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a particular voltage level and is not related
directly to the transition time of the positive-going pulse. When CLK is at either the high or low level, the D input has
no effect at the output.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Input clamp current, IIK (VI < 0 or VI > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
Output clamp current, IOK (VO < 0 or VO > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25 mA
Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Package thermal impedance, θJA (see Note 2): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70°C/W
DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58°C/W
N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69°C/W
NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60°C/W
PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
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Wide Operating Voltage Range of 2 V to 6 V
Outputs Can Drive Up To 10 LSTTL Loads
Low Power Consumption, 80-μA Max ICC
Typical tpd = 12 ns
±4-mA Output Drive at 5 V
Low Input Current of 1 μA Max
Contain Eight Flip-Flops With Single-Rail
Outputs
Direct Clear Input
Individual Data Input to Each Flip-Flop
Applications Include:
− Buffer/Storage Registers
− Shift Registers
− Pattern Generators
description/ordering information
These circuits are positive-edge-triggered D-type flip-flops with a direct clear (CLR) input.
Information at the data (D) inputs meeting the setup time requirements is transferred to the Q outputs on the
positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a particular voltage level and is not related
directly to the transition time of the positive-going pulse. When CLK is at either the high or low level, the D input has
no effect at the output.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Input clamp current, IIK (VI < 0 or VI > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
Output clamp current, IOK (VO < 0 or VO > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25 mA
Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Package thermal impedance, θJA (see Note 2): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70°C/W
DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58°C/W
N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69°C/W
NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60°C/W
PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
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SN54HC164, SN74HC164 Texas Instruments TI pdf datasheet download
SN54HC164, SN74HC164
8-BIT PARALLEL-OUT SERIAL SHIFT REGISTERS
Wide Operating Voltage Range of 2 V to 6 V
Outputs Can Drive Up To 10 LSTTL Loads
Low Power Consumption, 80-μA Max ICC
Typical tpd = 20 ns
±4-mA Output Drive at 5 V
Low Input Current of 1 μA Max
AND-Gated (Enable/Disable) Serial Inputs
Fully Buffered Clock and Serial Inputs
Direct Clear
description/ordering information
These 8-bit shift registers feature AND-gated
serial inputs and an asynchronous clear (CLR)
input. The gated serial (A and B) inputs permit
complete control over incoming data; a low at
either input inhibits entry of the new data and
resets the first flip-flop to the low level at the next
clock (CLK) pulse. A high-level input enables the
other input, which then determines the state of the
first flip-flop. Data at the serial inputs can be
changed while CLK is high or low, provided the
minimum setup time requirements are met.
Clocking occurs on the low-to-high-level transition
of CLK.
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8-BIT PARALLEL-OUT SERIAL SHIFT REGISTERS
Wide Operating Voltage Range of 2 V to 6 V
Outputs Can Drive Up To 10 LSTTL Loads
Low Power Consumption, 80-μA Max ICC
Typical tpd = 20 ns
±4-mA Output Drive at 5 V
Low Input Current of 1 μA Max
AND-Gated (Enable/Disable) Serial Inputs
Fully Buffered Clock and Serial Inputs
Direct Clear
description/ordering information
These 8-bit shift registers feature AND-gated
serial inputs and an asynchronous clear (CLR)
input. The gated serial (A and B) inputs permit
complete control over incoming data; a low at
either input inhibits entry of the new data and
resets the first flip-flop to the low level at the next
clock (CLK) pulse. A high-level input enables the
other input, which then determines the state of the
first flip-flop. Data at the serial inputs can be
changed while CLK is high or low, provided the
minimum setup time requirements are met.
Clocking occurs on the low-to-high-level transition
of CLK.
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Saturday, September 22, 2012
sn74hc139 Texas Instruments TI pdf datasheet download
sn74hc139.pdf
Targeted Specifically for High-Speed
Memory Decoders and Data-Transmission
Systems
Wide Operating Voltage Range of 2 V to 6 V
Outputs Can Drive Up To 10 LSTTL Loads
Low Power Consumption, 80-μA Max ICC
Typical tpd = 10 ns
±4-mA Output Drive at 5 V
Low Input Current of 1 μA Max
Incorporate Two Enable Inputs to Simplify
Cascading and/or Data Reception
description/ordering information
The ’HC139 devices are designed for
high-performance memory-decoding or
data-routing applications requiring very short
propagation delay times. In high-performance
memory systems, these decoders can minimize
the effects of system decoding. When employed
with high-speed memories utilizing a fast enable
circuit, the delay time of these decoders and the
enable time of the memory usually are less than
the typical access time of the memory. This means
that the effective system delay introduced by the
decoders is negligible.
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Targeted Specifically for High-Speed
Memory Decoders and Data-Transmission
Systems
Wide Operating Voltage Range of 2 V to 6 V
Outputs Can Drive Up To 10 LSTTL Loads
Low Power Consumption, 80-μA Max ICC
Typical tpd = 10 ns
±4-mA Output Drive at 5 V
Low Input Current of 1 μA Max
Incorporate Two Enable Inputs to Simplify
Cascading and/or Data Reception
description/ordering information
The ’HC139 devices are designed for
high-performance memory-decoding or
data-routing applications requiring very short
propagation delay times. In high-performance
memory systems, these decoders can minimize
the effects of system decoding. When employed
with high-speed memories utilizing a fast enable
circuit, the delay time of these decoders and the
enable time of the memory usually are less than
the typical access time of the memory. This means
that the effective system delay introduced by the
decoders is negligible.
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SN54ALS574B, SN54AS574, SN54AS575 SN74ALS574B, SN74ALS575A, SN74AS574, SN74AS575 Texas Instruments TI pdf datasheet download
SN54ALS574B, SN54AS574, SN54AS575
SN74ALS574B, SN74ALS575A, SN74AS574, SN74AS575
OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS WITH 3-STATE OUTPUTS
• 3-State Buffer-Type Noninverting Outputs
Drive Bus Lines Directly
• Bus-Structured Pinout
• Buffered Control Inputs
• SN74ALS575A and 4AS575 Have
Synchronous Clear
• Package Options Include Plastic
Small-Outline (DW) Packages, Ceramic
Chip Carriers (FK), Standard Plastic (N, NT)
and Ceramic (J, JT) 300-mil DIPs, and
Ceramic Flat (W) Packages
description
These octal D-type edge-triggered flip-flops
feature 3-state outputs designed specifically for
bus driving. They are particularly suitable for
implementing buffer registers, I/O ports,
bidirectional bus drivers, and working registers.
The eight flip-flops enter data on the low-to-high
transition of the clock (CLK) input. The
SN74ALS575A, SN54AS575, and SN74AS575
may be synchronously cleared by taking the clear
(CLR) input low.
The output-enable (OE) input does not affect
internal operations of the flip-flops. Old data can
be retained or new data can be entered while the
outputs are in the high-impedance state.
The SN54ALS574B, SN54AS574, and
SN54AS575 are characterized for operation over
the full military temperature range of –55°C to
125°C. The SN74ALS574B, SN74ALS575A,
SN74AS574, and SN74AS575 are characterized
for operation from 0°C to 70°C.
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SN74ALS574B, SN74ALS575A, SN74AS574, SN74AS575
OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS WITH 3-STATE OUTPUTS
• 3-State Buffer-Type Noninverting Outputs
Drive Bus Lines Directly
• Bus-Structured Pinout
• Buffered Control Inputs
• SN74ALS575A and 4AS575 Have
Synchronous Clear
• Package Options Include Plastic
Small-Outline (DW) Packages, Ceramic
Chip Carriers (FK), Standard Plastic (N, NT)
and Ceramic (J, JT) 300-mil DIPs, and
Ceramic Flat (W) Packages
description
These octal D-type edge-triggered flip-flops
feature 3-state outputs designed specifically for
bus driving. They are particularly suitable for
implementing buffer registers, I/O ports,
bidirectional bus drivers, and working registers.
The eight flip-flops enter data on the low-to-high
transition of the clock (CLK) input. The
SN74ALS575A, SN54AS575, and SN74AS575
may be synchronously cleared by taking the clear
(CLR) input low.
The output-enable (OE) input does not affect
internal operations of the flip-flops. Old data can
be retained or new data can be entered while the
outputs are in the high-impedance state.
The SN54ALS574B, SN54AS574, and
SN54AS575 are characterized for operation over
the full military temperature range of –55°C to
125°C. The SN74ALS574B, SN74ALS575A,
SN74AS574, and SN74AS575 are characterized
for operation from 0°C to 70°C.
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Thursday, September 20, 2012
SN74LVC1G66 Texas Instruments TI pdf datasheet download
SN74LVC1G66
SINGLE BILATERAL ANALOG SWITCH
FEATURES
2• Available in the Texas Instruments NanoFree™ Package
• Low On-State Resistance, Typically ≉5.5 Ω
(VCC = 4.5 V)
• 1.65-V to 5.5-V VCC Operation
• Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
• Inputs Accept Voltages to 5.5 V
• Max tpd of 0.8 ns at 3.3 V
• High On-Off Output Voltage Ratio
• High Degree of Linearity
• High Speed, Typically 0.5 ns
(VCC = 3 V, CL = 50 pF)
• ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
DESCRIPTION/ORDERING INFORMATION
This single analog switch is designed for 1.65-V to 5.5-V VCC operation.
The SN74LVC1G66 can handle both analog and digital signals. The device permits signals with amplitudes of up
to 5.5 V (peak) to be transmitted in either direction.
NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the
package.
Applications include signal gating, chopping, modulation or demodulation (modem), and signal multiplexing for
analog-to-digital and digital-to-analog conversion systems.
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SINGLE BILATERAL ANALOG SWITCH
FEATURES
2• Available in the Texas Instruments NanoFree™ Package
• Low On-State Resistance, Typically ≉5.5 Ω
(VCC = 4.5 V)
• 1.65-V to 5.5-V VCC Operation
• Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
• Inputs Accept Voltages to 5.5 V
• Max tpd of 0.8 ns at 3.3 V
• High On-Off Output Voltage Ratio
• High Degree of Linearity
• High Speed, Typically 0.5 ns
(VCC = 3 V, CL = 50 pF)
• ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
DESCRIPTION/ORDERING INFORMATION
This single analog switch is designed for 1.65-V to 5.5-V VCC operation.
The SN74LVC1G66 can handle both analog and digital signals. The device permits signals with amplitudes of up
to 5.5 V (peak) to be transmitted in either direction.
NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the
package.
Applications include signal gating, chopping, modulation or demodulation (modem), and signal multiplexing for
analog-to-digital and digital-to-analog conversion systems.
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Monday, August 6, 2012
MC1489, MC1489A, SN55189, SN55189A, SN75189, SN75189A
MC1489, MC1489A, SN55189, SN55189A, SN75189, SN75189A
QUADRUPLE LINE RECEIVERS
Input Resistance . . . 3 kW to 7 kW
Input Signal Range . . . ±30 V
Operate From Single 5-V Supply
Built-In Input Hysteresis (Double
Thresholds)
Response Control that Provides:
Input Threshold Shifting
Input Noise Filtering
Meet or Exceed the Requirements of
TIA/EIA-232-F and ITU Recommendation
V.28
Fully Interchangeable With MotorolaE
MC1489 and MC1489A
description
These devices are monolithic low-power Schottky
quadruple line receivers designed to satisfy the
requirements of the standard interface between
data-terminal equipment and data-communication
equipment as defined by TIA/EIA-232-F. A
separate response-control (CONT) terminal is
provided for each receiver. A resistor or a resistor
and bias-voltage source can be connected
between this terminal and ground to shift the input
threshold levels. An external capacitor can be
connected between this terminal and ground to
provide input noise filtering.
The SN55189 and SN55189A are characterized
for operation over the full military temperature
range of –55°C to 125°C. The MC1489,
MC1489A, SN75189, and SN75189A are
characterized for operation from 0°C to 70°C.
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QUADRUPLE LINE RECEIVERS
Input Resistance . . . 3 kW to 7 kW
Input Signal Range . . . ±30 V
Operate From Single 5-V Supply
Built-In Input Hysteresis (Double
Thresholds)
Response Control that Provides:
Input Threshold Shifting
Input Noise Filtering
Meet or Exceed the Requirements of
TIA/EIA-232-F and ITU Recommendation
V.28
Fully Interchangeable With MotorolaE
MC1489 and MC1489A
description
These devices are monolithic low-power Schottky
quadruple line receivers designed to satisfy the
requirements of the standard interface between
data-terminal equipment and data-communication
equipment as defined by TIA/EIA-232-F. A
separate response-control (CONT) terminal is
provided for each receiver. A resistor or a resistor
and bias-voltage source can be connected
between this terminal and ground to shift the input
threshold levels. An external capacitor can be
connected between this terminal and ground to
provide input noise filtering.
The SN55189 and SN55189A are characterized
for operation over the full military temperature
range of –55°C to 125°C. The MC1489,
MC1489A, SN75189, and SN75189A are
characterized for operation from 0°C to 70°C.
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SN74LVC1G3157 Texas Instruments, pdf datasheet download
SN74LVC1G3157
SINGLE-POLE DOUBLE-THROW ANALOG SWITCH
FEATURES
• 1.65-V to 5.5-V VCC Operation
• Useful for Both Analog and Digital
Applications
• Specified Break-Before-Make Switching
• Rail-to-Rail Signal Handling
• High Degree of Linearity
• High Speed, Typically 0.5 ns
(VCC = 3 V, CL = 50 pF)
• Low On-State Resistance, Typically ≉6 Ω
(VCC = 4.5 V)
• Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
• ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
DESCRIPTION/ORDERING INFORMATION
This single-pole double-throw (SPDT) analog switch is designed for 1.65-V to 5.5-V VCC operation.
The SN74LVC1G3157 can handle both analog and digital signals. The device permits signals with amplitudes of
up to VCC (peak) to be transmitted in either direction.
Applications include signal gating, chopping, modulation or demodulation (modem), and signal multiplexing for
analog-to-digital and digital-to-analog conversion systems.
Click here to download Texas Instruments SN74LVC1G3157 pdf datasheet
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SINGLE-POLE DOUBLE-THROW ANALOG SWITCH
FEATURES
• 1.65-V to 5.5-V VCC Operation
• Useful for Both Analog and Digital
Applications
• Specified Break-Before-Make Switching
• Rail-to-Rail Signal Handling
• High Degree of Linearity
• High Speed, Typically 0.5 ns
(VCC = 3 V, CL = 50 pF)
• Low On-State Resistance, Typically ≉6 Ω
(VCC = 4.5 V)
• Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
• ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
DESCRIPTION/ORDERING INFORMATION
This single-pole double-throw (SPDT) analog switch is designed for 1.65-V to 5.5-V VCC operation.
The SN74LVC1G3157 can handle both analog and digital signals. The device permits signals with amplitudes of
up to VCC (peak) to be transmitted in either direction.
Applications include signal gating, chopping, modulation or demodulation (modem), and signal multiplexing for
analog-to-digital and digital-to-analog conversion systems.
Click here to download Texas Instruments SN74LVC1G3157 pdf datasheet
DatasheetDoc-All pdf datasheet download
slau263g MSP-EXP430F5438 Texas Instruments pdf datasheet download
MSP-EXP430F5438 Experimenter Board
User's Guide
1.1 MSP-EXP430F5438 Experimenter Board Introduction
The MSP-EXP430F5438 Experimenter Board is an evaluation board meant to evaluate the capabilities of
the MSP430F5438A family of microcontrollers. Built to complement the MSP430's high degree of
mixed-signal integration, the Experimenter Board showcases external peripherals such as a dot-matrix
LCD, two-axis accelerometer, microphone, audio output, a serial USB connection, and RF add-ons.
Delivered with an example software project to help firmware designers understand how to program the
new peripherals of the MSP430F5xx family of devices, there is no better way to learn how to use the
MSP430F5438A than with the MSP-EXP430F5438 Experimenter Board. This document details the
hardware, its use, and the example software.
1.2 Kit Contents
• 1 x MSP-EXP430F5438 Experimenter Board + AA Batteries
• 1 x 100-pin MSP430F5438AIPZ microcontroller [1]
SLAU263G–January 2009–Revised June 2011 Getting Started 9
Submit Documentation Feedback
Copyright © 2009–2011, Texas Instruments Incorporated
Tools Requirements www.ti.com
1.3 Tools Requirements
1.3.1 Hardware
An MSP430 Flash Emulation Tool (MSP-FET430UIF) or equivalent programming tool is required to
download code and debug the MSP430F5438A. The JTAG programmer is connected to the
MSP-EXP430F5438 Experimenter Board via the JTAG header located in the top center of the board. The
MSP430F5438A utilizes the standard 4-wire JTAG connection. For more details on the installation and
usage of the Flash Emulation Tool, see the MSP430 Hardware Tools User's Guide (SLAU278). [3]
1.3.2 Software
Texas Instruments' Code Composer Studio (CCS) is an MSP430 integrated development environment
(IDE) designed specifically to develop applications and program MSP430 devices. CCS, CCS Core
Edition, and IAR Embedded Workbench can all be used to evaluate the example software for the
Experimenter Board. The compiler limitation of 4 KB prevents IAR KickStart from being able to be used for
the evaluation of the example software.
The example software, titled "User Experience," is available online as MSP-EXP430F5438(A) Example
Software (SLAC227). The User Experience application must be loaded onto the MSP430F5438A that
comes with the kit and is documented in Chapter 5. When compiled and run using an IDE, the APIs that
have been included in the example software can be used to develop unique applications with the
Experimenter Board. The APIs can serve as interfaces to the internal hardware modules of the
MSP430F5438A (for example, ADC12 or UCS) as well as external peripherals and components (for
example, buttons or an LCD). Chapter 5 describes the steps required to compile and run the example
software using Code Composer Studio.
Click here to download Texas Instruments slau263g MSP-EXP430F5438 pdf datasheet
DatasheetDoc-All pdf datasheet download
User's Guide
1.1 MSP-EXP430F5438 Experimenter Board Introduction
The MSP-EXP430F5438 Experimenter Board is an evaluation board meant to evaluate the capabilities of
the MSP430F5438A family of microcontrollers. Built to complement the MSP430's high degree of
mixed-signal integration, the Experimenter Board showcases external peripherals such as a dot-matrix
LCD, two-axis accelerometer, microphone, audio output, a serial USB connection, and RF add-ons.
Delivered with an example software project to help firmware designers understand how to program the
new peripherals of the MSP430F5xx family of devices, there is no better way to learn how to use the
MSP430F5438A than with the MSP-EXP430F5438 Experimenter Board. This document details the
hardware, its use, and the example software.
1.2 Kit Contents
• 1 x MSP-EXP430F5438 Experimenter Board + AA Batteries
• 1 x 100-pin MSP430F5438AIPZ microcontroller [1]
SLAU263G–January 2009–Revised June 2011 Getting Started 9
Submit Documentation Feedback
Copyright © 2009–2011, Texas Instruments Incorporated
Tools Requirements www.ti.com
1.3 Tools Requirements
1.3.1 Hardware
An MSP430 Flash Emulation Tool (MSP-FET430UIF) or equivalent programming tool is required to
download code and debug the MSP430F5438A. The JTAG programmer is connected to the
MSP-EXP430F5438 Experimenter Board via the JTAG header located in the top center of the board. The
MSP430F5438A utilizes the standard 4-wire JTAG connection. For more details on the installation and
usage of the Flash Emulation Tool, see the MSP430 Hardware Tools User's Guide (SLAU278). [3]
1.3.2 Software
Texas Instruments' Code Composer Studio (CCS) is an MSP430 integrated development environment
(IDE) designed specifically to develop applications and program MSP430 devices. CCS, CCS Core
Edition, and IAR Embedded Workbench can all be used to evaluate the example software for the
Experimenter Board. The compiler limitation of 4 KB prevents IAR KickStart from being able to be used for
the evaluation of the example software.
The example software, titled "User Experience," is available online as MSP-EXP430F5438(A) Example
Software (SLAC227). The User Experience application must be loaded onto the MSP430F5438A that
comes with the kit and is documented in Chapter 5. When compiled and run using an IDE, the APIs that
have been included in the example software can be used to develop unique applications with the
Experimenter Board. The APIs can serve as interfaces to the internal hardware modules of the
MSP430F5438A (for example, ADC12 or UCS) as well as external peripherals and components (for
example, buttons or an LCD). Chapter 5 describes the steps required to compile and run the example
software using Code Composer Studio.
Click here to download Texas Instruments slau263g MSP-EXP430F5438 pdf datasheet
DatasheetDoc-All pdf datasheet download
Sunday, August 5, 2012
Texas Instruments SN65HVD230 SN65HVD231 SN65HVD232 pdf datasheet download
SN65HVD230
SN65HVD231
SN65HVD232
FEATURES
2• Operates With a 3.3-V Supply
• Low Power Replacement for the PCA82C250
Footprint
• Bus/Pin ESD Protection Exceeds 16 kV HBM
• High Input Impedance Allows for 120 Nodes on
a Bus
• Controlled Driver Output Transition Times for
Improved Signal Quality on the SN65HVD230
and SN65HVD231
• Unpowered Node Does Not Disturb the Bus
• Compatible With the Requirements of the ISO
11898 Standard
• Low-Current SN65HVD230 Standby Mode
370 μA Typical
• Low-Current SN65HVD231 Sleep Mode 40 nA
Typical
• Designed for Signaling Rates(1) up to 1
Megabit/Second (Mbps)
• Thermal Shutdown Protection
• Open-Circuit Fail-Safe Design
• Glitch-Free Power-Up and Power-Down
Protection for Hot-Plugging Applications
(1) The signaling rate of a line is the number of voltage
transitions that are made per second expressed in the units
bps (bits per second).
APPLICATIONS
• Motor Control
• Industrial Automation
• Basestation Control and Status
• Robotics
• Automotive
• UPS Control
DESCRIPTION
The SN65HVD230, SN65HVD231, and SN65HVD232 controller area network (CAN) transceivers are designed
for use with the Texas Instruments TMS320Lx240x™ ; 3.3-V DSPs with CAN controllers, or with
equivalent devices. They are intended for use in applications employing the CAN serial communication physical
layer in accordance with the ISO 11898 standard. Each CAN transceiver is designed to provide differential
transmit capability to the bus and differential receive capability to a CAN controller at speeds up to 1 Mbps.
Designed for operation in especially-harsh environments, these devices feature cross-wire protection,
loss-of-ground and overvoltage protection, overtemperature protection, as well as wide common-mode range.
The transceiver interfaces the single-ended CAN controller with the differential CAN bus found in industrial,
building automation, and automotive applications. It operates over a -2-V to 7-V common-mode range on the
bus, and it can withstand common-mode transients of ±25 V.
On the SN65HVD230 and SN65HVD231, pin 8 provides three different modes of operation: high-speed, slope
control, and low-power modes. The high-speed mode of operation is selected by connecting pin 8 to ground,
allowing the transmitter output transistors to switch on and off as fast as possible with no limitation on the rise
and fall slopes. The rise and fall slopes can be adjusted by connecting a resistor to ground at pin 8, since the
slope is proportional to the pin's output current. This slope control is implemented with external resistor values of
10 kΩ, to achieve a 15-V/μs slew rate, to 100 kΩ, to achieve a 2-V/μs slew rate. See the Application Information
section of this data sheet.
The circuit of the SN65HVD230 enters a low-current standby mode during which the driver is switched off and
the receiver remains active if a high logic level is applied to pin 8. The DSP controller reverses this low-current
standby mode when a dominant state (bus differential voltage > 900 mV typical) occurs on the bus.
The unique difference between the SN65HVD230 and the SN65HVD231 is that both the driver and the receiver
are switched off in the SN65HVD231 when a high logic level is applied to pin 8 and remain in this sleep mode
until the circuit is reactivated by a low logic level on pin 8.
The Vref pin 5 on the SN65HVD230 and SN65HVD231 is available as a VCC/2 voltage reference.
The SN65HVD232 is a basic CAN transceiver with no added options; pins 5 and 8 are NC, no connection.
Click here to download Texas Instruments SN65HVD230 SN65HVD231 SN65HVD232 pdf datasheet
DatasheetDoc-All pdf datasheet download
SN65HVD231
SN65HVD232
FEATURES
2• Operates With a 3.3-V Supply
• Low Power Replacement for the PCA82C250
Footprint
• Bus/Pin ESD Protection Exceeds 16 kV HBM
• High Input Impedance Allows for 120 Nodes on
a Bus
• Controlled Driver Output Transition Times for
Improved Signal Quality on the SN65HVD230
and SN65HVD231
• Unpowered Node Does Not Disturb the Bus
• Compatible With the Requirements of the ISO
11898 Standard
• Low-Current SN65HVD230 Standby Mode
370 μA Typical
• Low-Current SN65HVD231 Sleep Mode 40 nA
Typical
• Designed for Signaling Rates(1) up to 1
Megabit/Second (Mbps)
• Thermal Shutdown Protection
• Open-Circuit Fail-Safe Design
• Glitch-Free Power-Up and Power-Down
Protection for Hot-Plugging Applications
(1) The signaling rate of a line is the number of voltage
transitions that are made per second expressed in the units
bps (bits per second).
APPLICATIONS
• Motor Control
• Industrial Automation
• Basestation Control and Status
• Robotics
• Automotive
• UPS Control
DESCRIPTION
The SN65HVD230, SN65HVD231, and SN65HVD232 controller area network (CAN) transceivers are designed
for use with the Texas Instruments TMS320Lx240x™ ; 3.3-V DSPs with CAN controllers, or with
equivalent devices. They are intended for use in applications employing the CAN serial communication physical
layer in accordance with the ISO 11898 standard. Each CAN transceiver is designed to provide differential
transmit capability to the bus and differential receive capability to a CAN controller at speeds up to 1 Mbps.
Designed for operation in especially-harsh environments, these devices feature cross-wire protection,
loss-of-ground and overvoltage protection, overtemperature protection, as well as wide common-mode range.
The transceiver interfaces the single-ended CAN controller with the differential CAN bus found in industrial,
building automation, and automotive applications. It operates over a -2-V to 7-V common-mode range on the
bus, and it can withstand common-mode transients of ±25 V.
On the SN65HVD230 and SN65HVD231, pin 8 provides three different modes of operation: high-speed, slope
control, and low-power modes. The high-speed mode of operation is selected by connecting pin 8 to ground,
allowing the transmitter output transistors to switch on and off as fast as possible with no limitation on the rise
and fall slopes. The rise and fall slopes can be adjusted by connecting a resistor to ground at pin 8, since the
slope is proportional to the pin's output current. This slope control is implemented with external resistor values of
10 kΩ, to achieve a 15-V/μs slew rate, to 100 kΩ, to achieve a 2-V/μs slew rate. See the Application Information
section of this data sheet.
The circuit of the SN65HVD230 enters a low-current standby mode during which the driver is switched off and
the receiver remains active if a high logic level is applied to pin 8. The DSP controller reverses this low-current
standby mode when a dominant state (bus differential voltage > 900 mV typical) occurs on the bus.
The unique difference between the SN65HVD230 and the SN65HVD231 is that both the driver and the receiver
are switched off in the SN65HVD231 when a high logic level is applied to pin 8 and remain in this sleep mode
until the circuit is reactivated by a low logic level on pin 8.
The Vref pin 5 on the SN65HVD230 and SN65HVD231 is available as a VCC/2 voltage reference.
The SN65HVD232 is a basic CAN transceiver with no added options; pins 5 and 8 are NC, no connection.
Click here to download Texas Instruments SN65HVD230 SN65HVD231 SN65HVD232 pdf datasheet
DatasheetDoc-All pdf datasheet download
Texas Instruments SN65HVD230 SN65HVD231 SN65HVD232 pdf datasheet download
SN65HVD230
SN65HVD231
SN65HVD232
FEATURES
2• Operates With a 3.3-V Supply
• Low Power Replacement for the PCA82C250
Footprint
• Bus/Pin ESD Protection Exceeds 16 kV HBM
• High Input Impedance Allows for 120 Nodes on
a Bus
• Controlled Driver Output Transition Times for
Improved Signal Quality on the SN65HVD230
and SN65HVD231
• Unpowered Node Does Not Disturb the Bus
• Compatible With the Requirements of the ISO
11898 Standard
• Low-Current SN65HVD230 Standby Mode
370 μA Typical
• Low-Current SN65HVD231 Sleep Mode 40 nA
Typical
• Designed for Signaling Rates(1) up to 1
Megabit/Second (Mbps)
• Thermal Shutdown Protection
• Open-Circuit Fail-Safe Design
• Glitch-Free Power-Up and Power-Down
Protection for Hot-Plugging Applications
(1) The signaling rate of a line is the number of voltage
transitions that are made per second expressed in the units
bps (bits per second).
APPLICATIONS
• Motor Control
• Industrial Automation
• Basestation Control and Status
• Robotics
• Automotive
• UPS Control
DESCRIPTION
The SN65HVD230, SN65HVD231, and SN65HVD232 controller area network (CAN) transceivers are designed
for use with the Texas Instruments TMS320Lx240x™ ; 3.3-V DSPs with CAN controllers, or with
equivalent devices. They are intended for use in applications employing the CAN serial communication physical
layer in accordance with the ISO 11898 standard. Each CAN transceiver is designed to provide differential
transmit capability to the bus and differential receive capability to a CAN controller at speeds up to 1 Mbps.
Designed for operation in especially-harsh environments, these devices feature cross-wire protection,
loss-of-ground and overvoltage protection, overtemperature protection, as well as wide common-mode range.
The transceiver interfaces the single-ended CAN controller with the differential CAN bus found in industrial,
building automation, and automotive applications. It operates over a -2-V to 7-V common-mode range on the
bus, and it can withstand common-mode transients of ±25 V.
On the SN65HVD230 and SN65HVD231, pin 8 provides three different modes of operation: high-speed, slope
control, and low-power modes. The high-speed mode of operation is selected by connecting pin 8 to ground,
allowing the transmitter output transistors to switch on and off as fast as possible with no limitation on the rise
and fall slopes. The rise and fall slopes can be adjusted by connecting a resistor to ground at pin 8, since the
slope is proportional to the pin's output current. This slope control is implemented with external resistor values of
10 kΩ, to achieve a 15-V/μs slew rate, to 100 kΩ, to achieve a 2-V/μs slew rate. See the Application Information
section of this data sheet.
The circuit of the SN65HVD230 enters a low-current standby mode during which the driver is switched off and
the receiver remains active if a high logic level is applied to pin 8. The DSP controller reverses this low-current
standby mode when a dominant state (bus differential voltage > 900 mV typical) occurs on the bus.
The unique difference between the SN65HVD230 and the SN65HVD231 is that both the driver and the receiver
are switched off in the SN65HVD231 when a high logic level is applied to pin 8 and remain in this sleep mode
until the circuit is reactivated by a low logic level on pin 8.
The Vref pin 5 on the SN65HVD230 and SN65HVD231 is available as a VCC/2 voltage reference.
The SN65HVD232 is a basic CAN transceiver with no added options; pins 5 and 8 are NC, no connection.
Click here to download Texas Instruments SN65HVD230 SN65HVD231 SN65HVD232 pdf datasheet
DatasheetDoc-All pdf datasheet download
SN65HVD231
SN65HVD232
FEATURES
2• Operates With a 3.3-V Supply
• Low Power Replacement for the PCA82C250
Footprint
• Bus/Pin ESD Protection Exceeds 16 kV HBM
• High Input Impedance Allows for 120 Nodes on
a Bus
• Controlled Driver Output Transition Times for
Improved Signal Quality on the SN65HVD230
and SN65HVD231
• Unpowered Node Does Not Disturb the Bus
• Compatible With the Requirements of the ISO
11898 Standard
• Low-Current SN65HVD230 Standby Mode
370 μA Typical
• Low-Current SN65HVD231 Sleep Mode 40 nA
Typical
• Designed for Signaling Rates(1) up to 1
Megabit/Second (Mbps)
• Thermal Shutdown Protection
• Open-Circuit Fail-Safe Design
• Glitch-Free Power-Up and Power-Down
Protection for Hot-Plugging Applications
(1) The signaling rate of a line is the number of voltage
transitions that are made per second expressed in the units
bps (bits per second).
APPLICATIONS
• Motor Control
• Industrial Automation
• Basestation Control and Status
• Robotics
• Automotive
• UPS Control
DESCRIPTION
The SN65HVD230, SN65HVD231, and SN65HVD232 controller area network (CAN) transceivers are designed
for use with the Texas Instruments TMS320Lx240x™ ; 3.3-V DSPs with CAN controllers, or with
equivalent devices. They are intended for use in applications employing the CAN serial communication physical
layer in accordance with the ISO 11898 standard. Each CAN transceiver is designed to provide differential
transmit capability to the bus and differential receive capability to a CAN controller at speeds up to 1 Mbps.
Designed for operation in especially-harsh environments, these devices feature cross-wire protection,
loss-of-ground and overvoltage protection, overtemperature protection, as well as wide common-mode range.
The transceiver interfaces the single-ended CAN controller with the differential CAN bus found in industrial,
building automation, and automotive applications. It operates over a -2-V to 7-V common-mode range on the
bus, and it can withstand common-mode transients of ±25 V.
On the SN65HVD230 and SN65HVD231, pin 8 provides three different modes of operation: high-speed, slope
control, and low-power modes. The high-speed mode of operation is selected by connecting pin 8 to ground,
allowing the transmitter output transistors to switch on and off as fast as possible with no limitation on the rise
and fall slopes. The rise and fall slopes can be adjusted by connecting a resistor to ground at pin 8, since the
slope is proportional to the pin's output current. This slope control is implemented with external resistor values of
10 kΩ, to achieve a 15-V/μs slew rate, to 100 kΩ, to achieve a 2-V/μs slew rate. See the Application Information
section of this data sheet.
The circuit of the SN65HVD230 enters a low-current standby mode during which the driver is switched off and
the receiver remains active if a high logic level is applied to pin 8. The DSP controller reverses this low-current
standby mode when a dominant state (bus differential voltage > 900 mV typical) occurs on the bus.
The unique difference between the SN65HVD230 and the SN65HVD231 is that both the driver and the receiver
are switched off in the SN65HVD231 when a high logic level is applied to pin 8 and remain in this sleep mode
until the circuit is reactivated by a low logic level on pin 8.
The Vref pin 5 on the SN65HVD230 and SN65HVD231 is available as a VCC/2 voltage reference.
The SN65HVD232 is a basic CAN transceiver with no added options; pins 5 and 8 are NC, no connection.
Click here to download Texas Instruments SN65HVD230 SN65HVD231 SN65HVD232 pdf datasheet
DatasheetDoc-All pdf datasheet download
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